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AN1471 APPLICATION NOTE
What Happens to the M24xxx IC EEPROM If the IC Bus Communication is Stopped?
This document describes what needs to be done to set an M24xxx device back to a known state if it has been suddenly stopped before completion of the current IC instruction, for example due to a power failure at the Bus Master. The answer can be structured under the following main headings, as summarised by the two cases shown in Figure 1:
s s
Case 1: VCC dropped below the Power on Reset threshold, VPOR Case 2: VCC dropped to a value between the minimum operating voltage and the Power on Reset threshold
Figure 1. Two Cases of VCC Falling out of its Specified Working Range
VCC VCC(max)
VCC(min)
VPOR
Case 1
Case 2
time
AI05715
The minimum operating voltage, V CC(min), is 4.5 V for a M24xxx, 2.5 V for a M24xxx-W, and 1.8 V for a M24xxx-S or M24xxx-R. The VPOR threshold is about 1.5 V. CASE 1: VCC DROPS BELOW THE POWER ON RESET THRESHOLD, VPOR Once VCC drops below VPOR, the M24xxx internal logic is frozen. When VCC rises again, and goes above the VPOR threshold, the M24xxx internal logic is reset to a known state (with the address counter initialized to 0), and the device is ready, while VCC is above VCC(min), to decode any newly incoming instructions.
November 2001
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CASE 2: VCC DROPS TO A VALUE BETWEEN THE MINIMUM OPERATING VOLTAGE AND THE POWER ON RESET THRESHOLD When VCC eventually recovers, to be within the specified voltage range (VCC(max)>V CC>VCC(min)), the internal state of the M24xxx is in an unknown state. The Bus Master (the microcontroller or processor) and other components might well have failed, with clock and data lines now being improperly driven. The M24xxx internal logic must be re-initialized. The analysis of this situation can be structured under the following sub-headings:
s s
The interrupted transmission was an Incoming Data Byte The interrupted transmission was an Outgoing Data Byte (during a READ cycle)
The interrupted transmission was an Incoming Data Byte The issue of a STOP condition is sufficient to abort the transmission. However, if the last transmitted instruction was a WRITE, the STOP condition is also able to start the internal Write cycle (if the STOP condition occurs after the 9th clock cycle). It is therefore risky to send a single STOP condition. It is recommended, instead, to issue a START condition first, followed by a STOP condition. The START condition aborts the transmission, and leaves the M24xxx waiting for a Device Select Code; the STOP condition then sets the M24xxx in stand-by mode. The internal address counter will not have been reset to 0 by this (unless VCC drops below the VPOR threshold). So the next instruction should not be a Current Read or Sequential Current Read, since neither of these defines an address. Instead, the next instruction must be a Byte Random Read, Sequential Random Read or Write. The interrupted transmission was an Outgoing Data Byte (during a READ cycle) Figure 2 shows the waveform of two overlapping trains of pulses, on SCL and SDA, that are recommended for the Bus Master to send to the M24xxx. This is not a standard sequence from the I2C protocol, but a specially designed sequence for clearing the device to a known state. The main part of the sequence consists of nine rising edges of SCL, interleaved with nine attempts by the Bus Master to force a falling edge on SDA while SCL is High. In this way, the Bus Master makes nine attempts at causing a START condition. It is certain to succeed on the nineth attempt, if not before, and can be followed by a STOP condition, thus putting the device in its known standby state. The reason for the possible failure of the previous eight attempts at causing a START condition is depicted in Figure 2. The M24xxx might have been left in a state in which it was part way through clocking out a byte on the SDA bus. If the bit to be clocked out is a zero, the memory device will hold the SDA line Low, thus preventing the Bus Master from putting a falling edge on this line. In the worst case, the memory device might be at the start of clocking out eight 0s, if the data byte has been 00h, as shown in Figure 2.
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Figure 2. Nine Attempts at a START Condition and then a STOP Condition
1 2 3 4 5 6 7 8 9
SCL from Bus Master SDAout from Bus Master SDAout from Memory Device
START Condition
0
0
0
0
0
0
0
0
NoACK
SDA Bus
AI02406b
Again, the internal address counter will not have been reset to 0 by this (unless VCC drops below the VPOR threshold). So the next instruction should not be a Current Read or Sequential Current Read, since neither of these defines an address. Instead, the next instruction must be a Byte Random Read, Sequential Random Read or Write. Universal Reset Sequence Conservatively, the method shown in Figure 2 will work regardless of whether the device had been stopped during an incoming byte transfer, or during an outgoing byte transfer. It can be used as a universal method of resetting the memory device whenever an undefined state has been detected to have occurred on the I2C bus.
STOP Condition
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For current information on ST products, please consult our pages on the world wide web: www.st.com If you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses:
apps.serial-flash@st.com ask.memory@st.com
(for application support) (for general enquiries)
Please remember to include your name, company, location, telephone number and fax number.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) November 2001 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Austalia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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